A vertical JFET with improved on to off current performance

Author

Meenu, T.V. ; Komaragiri, Rama

Author_Institution

Dept. of ECE, Nat. Inst. of Technol., Calicut, India

fYear

2013

fDate

4-6 June 2013

Firstpage

1

Lastpage

5

Abstract

This paper presents a vertical silicon-on-insulator enhancement mode junction field effect transistor (SOI JFET) for a better on to off current performance. A major problem limiting the scaling of bulk silicon CMOS is the diminished improvement in on current and the increase in off current. The short channel effects associated with MOSFET are a serious limitation for the scaling. The main problem of decreased on to off current performance can be overcome by using a SOI JFET. Here a 20nm SOI JFET (in 2D) has been analyzed using MEDICI^® (a Synopsis^® 2D-device simulation tool).

Keywords

CMOS integrated circuits; MOSFET; junction gate field effect transistors; silicon-on-insulator; MEDICI^®; MOSFET; SOI JFET; bulk silicon CMOS; improved on to off current performance; short channel effects; vertical JFET; vertical silicon-on-insulator enhancement mode junction field effect transistor; JFETs; Junctions; Logic gates; Silicon; Substrates; Threshold voltage; Junction field effect transistor (JFET); SOI JFET; on to off current ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging Research Areas and 2013 International Conference on Microelectronics, Communications and Renewable Energy (AICERA/ICMiCR), 2013 Annual International Conference on

Conference_Location

Kanjirapally

Print_ISBN

978-1-4673-5150-8

Type

conf

DOI

10.1109/AICERA-ICMiCR.2013.6575962

Filename

6575962