DocumentCode
285334
Title
Bounding the test sequence length of sequential circuits by the partial scan design
Author
Kunzmann, Arno B.
Author_Institution
Dept. Microelectron. Syst. Design, Karlsruhe Univ., Germany
Volume
1
fYear
1992
fDate
10-13 May 1992
Firstpage
435
Abstract
The selection of a minimal number of scan elements so that the necessary test sequence length can be kept below a given limit, thus bounding the test generation effort for the resulting sequential circuit, is addressed. The selection strategy is based on a calculus for the estimation of the maximum test sequence length, consisting of over 20 rules. Experimental results with the ISCAS-89 benchmark circuits show the efficiency of this approach
Keywords
boundary scan testing; logic testing; sequential circuits; ISCAS-89 benchmark circuits; calculus; efficiency; minimal number; partial scan design; scan elements; sequential circuits; test sequence length; Calculus; Circuit faults; Circuit testing; Circuit topology; Design for testability; Hardware; Performance evaluation; Sequential analysis; Sequential circuits; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0593-0
Type
conf
DOI
10.1109/ISCAS.1992.229920
Filename
229920
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