Hierarchical test generation and diagnostics of differential cascode voltage switch circuits

Hierarchical methodologies for design-for-testability, test generation, and fault modeling of digital (DCVS) circuits are described. In addition to the 2× density and speed advantages over the conventional CMOS circuits, DCVS technology also has the following improved features: (1) DCVS can handle the test generation for an unlimited size chip. The testing problem is reduced to that of a logic group, and CPU time increases linearly as the number of logic groups increases. Fewer test patterns are required than for a CMOS chip of the same function. (2) Using different levels of diagnostics, DCVS can perform an exact diagnostic to a logic group, a logic tree, or a logic gate level. (3) A self-testable logic design can be easily implemented in DCVS by connecting outputs of each logic group with an XOR tree