Verification and debugging of IDDQ test of low power chips

Quiescent supply current (I_DDQ) is a very effective test method for CMOS circuits. However, I_DDQ vector verification and debugging may take considerable time and effort; various problems have been encountered in this process, so different tools and methodologies have been devised to address them. For pre-silicon I_DDQ vector verification, a modular approach is adopted. I_DDQ is estimated for each vector based on leakage libraries of cells, and cell constraints can be verified automatically. For post-silicon I_DDQ vector issues, methods and analysis tools have been developed to identify the root causes. Scan cell and net value analysis will identify critical scan cells and nets, which will determine whether an I_DDQ pattern passes or fails, thus revealing the source of the extra leakage. These methodologies are proven to be very successful for I_DDQ vector debug and I_DDQ diagnosis.