Calculation of average and variance bus currents for reliability analysis of VLSI CMOS circuits

Techniques for calculating average and variance of currents in various branches of power and ground buses are presented. These current estimates can be used to estimate mean time to failure due to electromigration in sections of the buses and to redesign them, if necessary, so that the electromigration failures over the estimated lifespan of the chip are minimized. The validity of the approach rests on the assumption that the bus can be modeled as a linear resistive network. The sparsity of this network is exploited to speed up the calculation of averages and variances. It is necessary to formulate and LU factorize the node admittance matrix only once