Design and VLSI architecture of wave digital filters with short signed digit coefficients

The low-roundoff-noise properties of wave digital filters have known and desirable properties with respect to their realization with short coefficient wordlengths. The authors seek realizations with coefficients that are restricted to a particular form; the aim is to minimize the number of levels of addition required in the implementation of the two-port adaptor equations. Various types of short-word length signed-digit coefficients are investigated. A pole-zero analysis method gives an indication of the range of specifications that can be met for each type. A useful four-digit form is identified, and a four-level architecture for the associated two-port adaptor is developed. Direct and bit-level pipelined techniques are examined for its implementation. It is concluded that low-latency, high-clock-rate adaptors that can be employed in filters for high-performance applications can be designed with this method