• DocumentCode
    2854062
  • Title

    At-speed scan tests: Reality or fantasy?

  • Author

    Patil, Srinivas

  • Author_Institution
    Validation and Test Solutions, Intel Corporation, Austin, Texas, USA
  • fYear
    2007
  • fDate
    21-26 Oct. 2007
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    For almost two decades, at-speed scan tests have been actively pursued as a manufacturing test methodology in industry, and as an active field of research in academia. However, there is continued debate on the value and applicability of at-speed scan tests, specifically whether they will enable us to replace or significantly mitigate the need for at-speed functional tests. Numerous barriers still exist in the realization of this goal. The primary contributors to this barrier are design constraints (logical, timing and electrical) and the lack of comprehensive quality metrics beyond gross transition/path delay fault coverage. Besides the applicability of scan at-speed tests in screening subtle speed-dependent manufacturing defects, it is not clear if such tests have the resolution to address speed binning. Till such barriers to adoption of at-speed scan are lowered or overcome, at-speed scan as a universally applicable push-button methodology for comprehensive delay testing will remain a fantasy.
  • Keywords
    Rated frequency; delay test quality; delay tests; functional tests; overkill; scan-based at-speed tests; speed binning;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2007. ITC 2007. IEEE International
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1089-3539
  • Print_ISBN
    978-1-4244-1127-6
  • Type

    conf

  • DOI
    10.1109/TEST.2007.4437671
  • Filename
    4437671