Using adjacent sampling for error correcting analog-to-digital converters

The authors address the use of neighboring samples to linearize the behavior of high-speed flash analog-to-digital converters (ADCs). A novel converter architecture is proposed in which a single flash comparator bank and dual latch/encoder stages allow samples to be taken at intervals much smaller than the sampling period. The result is a calibration/compensation procedure which is less sensitive to calibration frequency than are previous schemes. Using two TRW-1025 converters to implement the architecture shows an improvement in the spurious free dynamic range of between 10 dB and 20 dB over the majority of the Nyquist band