DocumentCode
2855035
Title
Boolean minimization and algebraic factorization procedures for fully testable sequential machines
Author
Devadas, S. ; Keutzer, K.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
fYear
1989
fDate
5-9 Nov. 1989
Firstpage
208
Lastpage
211
Abstract
The authors present a novel Boolean minimization procedure of prime-implicant generation and constrained covering based on the Quine-McCluskey algorithm. On completion, it guarantees a prime and irredundant, fully testable Moore or Mealy finite state machine. Given a two-level circuit with these properties, constrained algebraic factorization techniques are used that retain the invariant that no single fault can both produce an invalid state and corrupt the distinguishing sequence by which that invalid state is detected. Besides offering a more detailed understanding of the sources of untestability in sequential circuits than previous approaches, this approach offers significant practical advantages as well. It is applicable to a wider range of circuits than optimal synthesis procedures whose utility is often limited by prohibitively high CPU requirements, and its less restrictive synthesis constraints result in lower area overhead than other constrained synthesis approaches. These observations are supported by experimental results.<>
Keywords
Boolean functions; finite automata; formal logic; logic CAD; logic testing; minimisation of switching nets; sequential circuits; Boolean minimization; Mealy finite state machine; Moore finite state machine; Quine-McCluskey algorithm; constrained algebraic factorization; logic CAD; optimal synthesis; prime-implicant generation; sequential circuits; testable sequential machines; two-level circuit; Circuit faults; Circuit testing; Feedback; Logic circuits; Logic testing; Minimization; Paper technology; Radio access networks; Rails; Sequential analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-1986-4
Type
conf
DOI
10.1109/ICCAD.1989.76937
Filename
76937
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