Title :
State assignment for multilevel logic using dynamic literal estimation
Author :
Bolotski, M. ; Camporese, D. ; Barman, R.
Author_Institution :
Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
Abstract :
The problem of assigning a representation for the states in a finite-state machine (FSM) so as to minimize the area required for implementation using multilevel logic is considered. The problem is reduced to one of minimizing the literal count in the combinational logic part of the FSM. Heuristics are used to guide the selection of candidate state assignments, and a fast literal estimator is used to choose the best assignment from among the candidates. This approach is compared to the mustang program and is found to produce, on average, smaller literal counts than mustang.<>
Keywords :
combinatorial circuits; finite automata; logic CAD; logic testing; minimisation; combinational logic part; dynamic literal estimation; finite-state machine; heuristics; literal count; minimisation; multilevel logic; state assignment; Automata; Circuit synthesis; Computer networks; Costs; Encoding; Equations; Libraries; Minimization; Programmable logic arrays; State estimation;
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
DOI :
10.1109/ICCAD.1989.76940
