Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays

Fault detection and fault-tolerance in modular processing arrays are reviving the use of majority voting techniques. In the present work, a study of a simple voting circuit structure, called a ratioed voter, proves its reliable operation when a dynamic N-modular redundant (DNMR) tuple is configured for testing in fault-tolerant processing arrays. Its application in VLSI design for self-testing would lead to a low area overhead and a high diagnosability, both contributing to improve yield. Moreover, the flexibility of such a structure, which allows modulating the voting level (N), permits a common approach for fabrication-time and on-line testing