DocumentCode
285633
Title
Improved test pattern generation for sequential circuits using implicit enumeration
Author
Auth, Elisabeth ; Kastner, Johannes
Author_Institution
Dept. of Electr. Eng., Tech. Univ. of Munich, Germany
Volume
3
fYear
1992
fDate
10-13 May 1992
Firstpage
1137
Abstract
The authors describe Essential, an efficient deterministic test pattern generation algorithm for synchronous sequential circuits. Its conceptual strategy is based on the combination of reverse time processing over time frames and forward processing within time frames. In addition to fully exploiting the beneficial methods that have successfully been used for combinational circuits by the ATG system SOCRATES, the proposed test generation approach comprises a new circuit model and several new techniques leading to a significant improvement and acceleration of the deterministic test pattern generation process
Keywords
logic CAD; logic testing; sequential circuits; Essential; SOCRATES; deterministic test pattern generation algorithm; forward processing; implicit enumeration; reverse time processing; synchronous sequential circuits; test pattern generation; Circuit faults; Circuit testing; Combinational circuits; Decision trees; Electronic design automation and methodology; Life estimation; Logic; Sequential circuits; Signal processing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0593-0
Type
conf
DOI
10.1109/ISCAS.1992.230326
Filename
230326
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