• DocumentCode
    2856476
  • Title

    A power-aware GALS architecture for real-time algorithm-specific tasks

  • Author

    Datta, Animesh ; Bhunia, Swarup ; Banerjee, Nilanjan ; Roy, Kaushik

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
  • fYear
    2005
  • fDate
    21-23 March 2005
  • Firstpage
    358
  • Lastpage
    363
  • Abstract
    We propose an adaptive scalable architecture suitable for performing real-time algorithm-specific tasks. The architecture is based on the globally asynchronous and locally synchronous (GALS) design paradigm. We demonstrate that for different real-time commercial applications with algorithm-specific jobs like online transaction processing, Fourier transform etc., the proposed architecture allows dynamic load-balancing and adaptive inter-task voltage scaling. The architecture can also detect process-shifts for the individual processing units and determine their appropriate operating conditions. Simulation results for two representative applications show that for a random job distribution, we obtain up to 67% improvement in MOPS/W (millions of operations per second per watt) over a fully synchronous implementation.
  • Keywords
    integrated circuit design; real-time systems; resource allocation; Fourier transform; adaptive inter-task voltage scaling; adaptive scalable architecture; dynamic load balancing; globally asynchronous and locally synchronous design; online transaction processing; power-aware GALS architecture; process shifts; random job distribution; real-time algorithm-specific tasks; Application software; Batteries; Clocks; Computer architecture; Degradation; Delay; Dynamic voltage scaling; Fourier transforms; Frequency; Limiting;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
  • Print_ISBN
    0-7695-2301-3
  • Type

    conf

  • DOI
    10.1109/ISQED.2005.12
  • Filename
    1410609