A novel approach for high-frequency gain-compensated sample-and-hold circuits

Presents a novel approach for the design of fast and accurate sample-and-hold circuits. The proposed architecture uses two low-gain transductance amplifiers which have their outputs connected together. The two amplifiers can be operated alternatively in an open-loop configuration and in a closed-loop configuration. The structure is equivalent to a unity-gain buffer using an operation amplifier with a DC open-loop gain which is equal to the product of the DC gains of the two stages. Offset contributions to the output voltage are also compensated. Results of a computer simulation of a sample-and hold circuit developed for a 1.2-μm CMOS technology are reported