Predicting and designing for the impact of process variations and mismatch on the trim range and yield of bandgap references

Process tolerance and device mismatch produce significant random variations in bandgap voltage reference circuits. These variations lead to errors in the reference voltage and significantly impact manufacturing cost by increasing trimming requirements and decreasing yield. Current-mirror mismatch, followed by V_BE spread, package shift, and resistor mismatch are the dominant sources of random error in bandgap reference circuits. A folded-cascode topology, often used in low voltage applications, can be optimized to effectively alleviate the effects of a mismatch in the mirroring devices. By decreasing the ratio of the current in the cascode to that of the bandgap core circuit and ascertaining the best-matched devices for implementing current-mirrors and current sources, these mismatches can be significantly reduced.