Modeling intrinsic fluctuations in decananometer MOS devices due to gate line edge roughness (LER)

Intra-die random fluctuation outcomes inherent to fabrication processes such as gate LER give rise to corresponding fluctuations in device characteristics. These fluctuations become significant for devices with channel length less than 50 nm, a feature size rapidly approaching practical interest. At this scale, the fringe electric field and the charge confinement near the interface play dominant roles in determining MOS device properties and their fluctuations. In this work, we first characterize LER as a lognormal probability density function (pdf) in spatial frequency. Then we apply a 3D quantum mechanically corrected variational principle (VQM) to obtain closed-form expressions for standard deviation of threshold voltage and device capacitance due to LER. Our approach provides a simple physics based alternative to the presently available TCAD simulation for investigating these complex issues as functions of gate size, oxide thickness, and channel doping level.