Rapid layout of a continuous-time transconductance-C filter

Author

Daasch, W.R. ; Wedlake, Martine

Author_Institution

Dept. of Electr. Eng., Portland State Univ., OR, USA

Volume

5

fYear

1992

fDate

10-13 May 1992

Firstpage

2256

Abstract

Recent results in the design automation of continuous-time transconductance-C filters are presented. These results are limited to grounded capacitors and are reported only for CMOS technologies. A high-level behavioral description of an LC ladder is outlined using a signal-flow graph technique. It is shown that a simple, four-line grammar provides enough versatility for several design generators to produce files for SPICE analysis and Magic layouts of the signal-flow graph simulation of the LC ladder. Areas of future work in these early stages of development of design automation of analog subsystems and circuits are suggested

Keywords

CMOS integrated circuits; active filters; circuit layout CAD; integrated circuit technology; ladder networks; linear integrated circuits; CMOS technologies; LC ladder; Magic layouts; SFG; SPICE analysis; analogue circuits; continuous-time; design automation; four-line grammar; grounded capacitors; high-level behavioral description; signal-flow graph technique; simulation; transconductance-C filter; Analytical models; CMOS technology; Capacitors; Circuit simulation; Design automation; Filters; SPICE; Signal analysis; Signal design; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0593-0

Type

conf

DOI

10.1109/ISCAS.1992.230510

Filename

230510