• DocumentCode
    2857785
  • Title

    200-gate ECL master-slice LSI

  • Author

    Masaki, A. ; Harada, Y. ; Chiba, T.

  • Author_Institution
    Hitachi Central Research Laboratory, Tokyo, Japan
  • Volume
    XVII
  • fYear
    1974
  • fDate
    15-13 Feb. 1974
  • Firstpage
    62
  • Lastpage
    63
  • Abstract
    A 200-gate ECL master slice LSI suitable for computer mainframe logic will be described. Optimization has resulted in a 1.5-ns loaded delay.2.5-W power dissipation and compatibility with standard ECL components.
  • Keywords
    Delay; Large scale integration; Logic circuits; Packaging; Pins; Power dissipation; Thermal resistance; Voltage; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1974 IEEE International
  • Conference_Location
    Philadelphia, PA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1974.1155336
  • Filename
    1155336
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2857785