Two self-timed handshake controllers for high speed applications

Self-timed circuits with an appropriate handshake control circuit (HCC) can be used to replace the global clock in a VLSI chip. The authors focus on designing a handshake controller with the highest frequency possible. The gain in speed results from the handshake protocol allowing certain constraints. The approaches taken in the two protocols, and the implementation, characteristics and constraints are discussed. The HCCs were rigorously tested by applying them to a bit-serial multiplier based on the modified Booth´s algorithm. Some results on the delay measurements of the HCCs and simulation results of the multipliers are presented