Automatic insertion of scan structure to enhance testability of embedded memories, cores and chips

This paper describes a technology independent test synthesis framework to enhance the testability of embedded memories, cores and chips using extended LSSD boundary scan methodology. Extended LSSD boundary scan reuses functional storage elements and therefore introduces minimal test logic overhead and delay. Automatic insertion of this DFT methodology is particularly challenging since it involves identification and reconfiguration of the functional latches and logic transformations of I/O cells. Experimental results demonstrate the productivity gained using the proposed test synthesis framework as well as the overlead induced by the proposed DFT method