• DocumentCode
    2859624
  • Title

    Stress testing FET gates without the use of test patterns

  • Author

    Puri, Y.

  • Author_Institution
    IBM System Development Division, Manassas, VA, USA
  • Volume
    XVIII
  • fYear
    1975
  • fDate
    27426
  • Firstpage
    86
  • Lastpage
    87
  • Abstract
    This paper will cover a technique for stressing of all FET gates in LSI dynamic random logic FET circuits. This is accomplished by reversing the sequence of the clock signals. No input test patterns are required.
  • Keywords
    Circuit testing; Clocks; Combinational circuits; FETs; Logic circuits; Logic devices; Logic gates; Logic testing; Stress; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1975 IEEE International
  • Type

    conf

  • DOI
    10.1109/ISSCC.1975.1155458
  • Filename
    1155458
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2859624