Distributed generation of weighted random patterns

Author

Savir, Jacob

Author_Institution

Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA

fYear

1998

fDate

26-30 Apr 1998

Firstpage

225

Lastpage

232

Abstract

A new weighted random pattern (WRP) design for testability (DFT) is described where the shift register latches (SRLs) distributed throughout the chip are modified so that they can generate biased pseudo-random patterns upon demand. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to “go after” the remaining untested faults. The cost and performance of this design system are explored on three pilot chips. Results of this experiment are provided in the paper

Keywords

automatic testing; built-in self test; design for testability; integrated circuit testing; logic testing; shift registers; BIST; biased pseudo-random patterns; design for testability; shift register latches; untested faults; weighted random patterns; Circuit faults; Circuit testing; Clocks; Costs; Design for testability; Distributed control; Fault detection; Jacobian matrices; Latches; Shift registers;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1998. Proceedings. 16th IEEE

Conference_Location

Monterey, CA

ISSN

1093-0167

Print_ISBN

0-8186-8436-4

Type

conf

DOI

10.1109/VTEST.1998.670872

Filename

670872