Development of a Real-Time Interpolator for NURBS Based on Multi-DSPs System

Author

Liu, N.

Author_Institution

Coll. of Inf. Sci. & Technol., Jinan Univ., Guangzhou

fYear

2006

fDate

24-26 May 2006

Firstpage

1

Lastpage

6

Abstract

On the analysis of current non-uniform rational B-spline (NURBS) interpolation studies, a configurable NURBS interpolation flows and a structure of two-phase pipeline mode interpolator which based on dual digital signal processor (DSP) is presented. With TMS32F2812 and TMSC6713 DSP chips, a test NURBS interpolator was built. Time delay indexes of the sub-algorithms included the configurable NURBS interpolation flows ware tested and the tasks scheduling strategy for the multi-DSPs interpolator is discussed. Experimental results showed that configurable NURBS interpolation flows are feasible and it can meet varied needs at tradeoff between speed and precision for different applications. The two-phase pipeline mode NURBS interpolator is successful to increase the interpolation speed

Keywords

delays; digital signal processing chips; interpolation; pipeline processing; splines (mathematics); DSP chips; NURBS; TMS32F2812; TMSC6713; digital signal processor; multiDSP system; nonuniform rational B-spline interpolation; real-time interpolator; tasks scheduling strategy; time delay indexes; two-phase pipeline mode interpolator; Digital signal processing chips; Digital signal processors; Interpolation; Pipelines; Real time systems; Signal analysis; Spline; Surface reconstruction; Surface topography; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Electronics and Applications, 2006 1ST IEEE Conference on

Conference_Location

Singapore

Print_ISBN

0-7803-9513-1

Electronic_ISBN

0-7803-9514-X

Type

conf

DOI

10.1109/ICIEA.2006.257290

Filename

4025891