Mixed-level VHDL simulation in the real world

Since designing with VHDL has become a reality, the true value of a top-down design methodology can finally be realised. Behavioural models can be written in VHDL without concern for implementation details. Then, as more detail is included, VHDL configurations allow the more detailed models to be substituted into the design without impacting the code that describes the rest of the system. VHDL´s unique behavioural abstraction and configuration flexibility is unmatched by any other HDL. The ability to provide an accelerated mixed-level simulation environment under a single consistent user interface, provides real value to the customer in terms of engineering productivity and the ability to control the design from top to bottom. With the levels of performance that this brings, total system verification is possible: verification of telecommunication systems from transmission start to screen verification of computer systems from OS boot to application execution, and verification of a project from start to finish