A simple method for forming sub-30 nm gate patterns with modified I-line double patterning technique

We present a simple modified double-patterning (DP) technique with I-line stepper to define 23 nm nano-scale structures and have successfully fabricated n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with gate length down to 69 nm. With this approach, polycrystalline silicon (poly-Si) gate with line width down to 70 nm could be formed with good control, which far exceeds the resolution limit of conventional I-line lithography.