Microprocessor Critical Design and Optimization

In this paper a 32-bit multithreaded RISC microprocessor is designed and optimized to perform data moving and processing in the high-performance Network Processor which is flexible to a wide variety of networking, communications, and other data-intensive products. As a critical part of network processor, the microprocessor mainly takes in charge of Internet Protocol (IP) packets´ transmitting. Forwarding logic is used to deal with the data hazard, and defer slots are used to deal with the control hazard, besides logic and physical optimizations are employed to solve timing of the critical path.