Study of temperature effects of mobility, swing, and early voltages on strained MOSFET devices

In addition to global stained epitaxial SiGe layer, silicon nitride as contact etching stop layer (CESL) is to be deposited on the whole device to enhance the straining effects. As found in this paper, 10μm/10μm (channel length/ width) PMOS devices at various temperatures with or without stain are referred. To focus on the SiGe alone, the 1.5nm silicon cap following epi-taxial SiGe is to be considered leaving the channel mainly SiGe. The mobility and swing are determined and compared with the control wafers without strained engineering. The variations of Early voltages at different temperatures are taken into account, too. Regularity of Early Voltage variations shows the potential implicit physical meanings as the strained engineering is to be applied.