Hardware and software-in-the-loop techniques using the OPNET modeling tool for JTRS developmental testing

This paper describes the continuation of the hardware-in-the-loop (HITL) project started by the U.S. Army Information Systems Engineering Command (ISEC) in FY 2000. The paper describes the design and implementation of a hardware-in-the-loop (HITL) and software-in-the-loop (SITL) methods using the discrete-event modeling package, OPNET modeler. The project objective is to develop a capability to evaluate performance of large and complex army communications networks and network-centric systems by combining virtual models with real networks. HITL and SITL methods have been developed that allow virtual models to communicate real IP traffic with real applications in real networks. A generic reference model for HITL and SITL use has been proposed for use in DoD systems. This paper proposes use of the HITL and SITL techniques for developmental testing for JTRS Cluster 1. Potential DoD programs that require developmental testing may be JTRS clusters, WIN-T, and FCS. The U.S. Army Information Systems Engineering Command (ISEC), Technology Integration Center (TIC), Fort Huachuca, AZ, and BAE SYSTEMS, CNIR, Reston, VA sponsored this research in the Computer Engineering Research Laboratory (CERL) at the University of Arizona.