Title :
A 25ns 4K static RAM
Author :
Jecmen, R. ; Ebel, A. ; Smith, R. ; Kynett, V. ; Chi-Hung Hui ; Pashley, R.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
Using device scaling, an N-channel MOS technology has been developed with minimum gate delays of less than 400ps. This paper will report on the design of 5V 1024b and 4096b RAMs with typical access times of 15ns and 25ns, respectively.
Keywords :
Added delay; Circuits; Current supplies; Decoding; Emergency power supplies; Power dissipation; Random access memory; Read-write memory; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1979 IEEE International
Conference_Location :
Philadelphia, PA, USA
DOI :
10.1109/ISSCC.1979.1155936
