DocumentCode
2867576
Title
An Integrated Quad-Core Opteron Processor
Author
Dorsey, J. ; Searles, S. ; Ciraula, M. ; Johnson, S. ; Bujanos, N. ; Wu, D. ; Braganza, M. ; Meyers, S. ; Fang, E. ; Kumar, R.
Author_Institution
AMD, Austin, TX
fYear
2007
fDate
11-15 Feb. 2007
Firstpage
102
Lastpage
103
Abstract
An integrated quad-core times86 processor is implemented in a 65nm 11M SOI CMOS process. Based on an enhanced Opterontrade core, the SoC-developed processor employs power- and thermal-management techniques throughout the design. The SRAM cache designs target process variation considerations and future process scalability. A DDR2/DDR3 combo-PHY and HT3 I/Os provide high-bandwidth interfaces.
Keywords
CMOS digital integrated circuits; SRAM chips; cache storage; integrated circuit design; logic design; low-power electronics; microprocessor chips; silicon-on-insulator; 65 nm; DDR2/DDR3 combo-PHY; HT3 I/O; Opteron core; SOI CMOS process; SRAM cache designs; integrated quad-core Opteron processor; power management; silicon-on-insulator; system-on-chip; thermal management; times86 processor; Circuit stability; Clocks; Delay; Error correction codes; Frequency; Phase locked loops; Read-write memory; Stress; Temperature sensors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0853-9
Electronic_ISBN
0193-6530
Type
conf
DOI
10.1109/ISSCC.2007.373608
Filename
4242285
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