DocumentCode
2867804
Title
The design of MOS dynamic RAMs
Author
Foss, R.
Author_Institution
Mosaid, Inc., Ottawa, Canada
Volume
XXII
fYear
1979
fDate
14-16 Feb. 1979
Firstpage
140
Lastpage
141
Abstract
The art of MOS RAM design involves the continuous compromise between layout area, performance criteria and internal safety margins. With each new generation, the tradeoffs become more difficult as less space is available for the circuits required to insure performance with safe operation. These trends are illustrated by 4K, 16K and now 64K circuit features.
Keywords
Circuit testing; Clocks; Coupling circuits; DRAM chips; High power amplifiers; Operational amplifiers; Random access memory; Read-write memory; Signal restoration; Writing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1979 IEEE International
Conference_Location
Philadelphia, PA, USA
Type
conf
DOI
10.1109/ISSCC.1979.1155961
Filename
1155961
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