Title :
A graph traversal based framework for sequential logic implication with an application to C-cycle redundancy identification
Author :
Zhao, Jian-Kun ; Newquist, Jefsrey A. ; Patel, Janak H.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
This paper presents a new graph traversal based framework for sequential logic implication called GRAPH-SIMP. Due to the prohibitive time and space cost, few previous works target the discovery of sequential indirect implications that span multiple time frames. By using an efficient graph data structure and incorporating a graph reduction step into the implication generation process, our approach provides an efficient support for sequential implication. Sequential logic implication has many useful applications, one of which is sequentially redundant fault identification. We show that sequential implications found by GRAPH SIMP allow us to find more sequential redundancies than previously reported. Results of testing our implication algorithm against ISCAS89 circuits show that high implication coverage is essential to identifying redundant faults
Keywords :
automatic test pattern generation; directed graphs; fault diagnosis; logic testing; redundancy; sequential circuits; C-cycle redundancy identification; GRAPH-SIMP; ISCAS89 circuits; graph data structure; graph reduction step; graph traversal based framework; implication generation process; multiple time frames; sequential logic; sequential logic implication; sequentially redundant fault identification; Automatic test pattern generation; Circuit analysis; Circuit faults; Circuit testing; Engines; Fault diagnosis; Laboratories; Logic circuits; Logic testing; Redundancy;
Conference_Titel :
VLSI Design, 2001. Fourteenth International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-7695-0831-6
DOI :
10.1109/ICVD.2001.902656