Optimal assignment of high threshold voltage for synthesizing dual threshold CMOS circuits

Author

Tripathi, Nikhil ; Bhosle, Amit ; Samanta, Debasis ; Pal, Ajit

Author_Institution

Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India

fYear

2001

fDate

2001

Firstpage

227

Lastpage

232

Abstract

Development of the process technology for dual threshold (dual V _th) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance circuits. It has been demonstrated that by using transistors of a low threshold voltage for gates on the critical path, and by using a high threshold voltage for gates in the off-critical path it is possible to significantly reduce leakage power consumption of a circuit without performance degradation. In this paper we have a new algorithm to realize dual CMOS circuits. Our algorithm produces significantly better results for ISCAS benchmark circuits compared to reported results

Keywords

CMOS logic circuits; circuit optimisation; delay estimation; integrated circuit design; leakage currents; power consumption; power supply circuits; ISCAS benchmark circuits; combinational circuit; delay estimation; dual threshold CMOS circuits; high threshold voltage; leakage power consumption; low threshold voltage; low voltage high performance circuits; off-critical path; optimal assignment; performance degradation; process technology; static power; CMOS process; CMOS technology; Circuit synthesis; Computer science; Degradation; Delay; Dynamic voltage scaling; Energy consumption; MOSFETs; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2001. Fourteenth International Conference on

Conference_Location

Bangalore

ISSN

1063-9667

Print_ISBN

0-7695-0831-6

Type

conf

DOI

10.1109/ICVD.2001.902665

Filename

902665