Software power optimizations in an embedded system

The topic of reducing power dissipation in embedded systems has received considerable attention in the recent years. Techniques have been reported to minimize energy dissipation through (a) selection of better algorithms for the application e.g. DSP algorithms that require fewer number of operations to perform a task such as filtering (b) minimizing state transitions and switching activity in the hardware implementation, and (c) reducing the operating supply voltage by changing the architecture of the system e.g. through the use of pipelining. However, power dissipation is often neglected when developing the software for embedded systems. Software optimization techniques can be used to reduce the cost, size, and power dissipation in embedded systems without adding to system overheads. In this paper, we view the power dissipation as consisting of two parts, the power dissipated in the application-specific integrated circuits (hardware power) and the power dissipated by the CPU, memory and associated busses (software power). We provide a trace-based technique to estimate software power and study the effect of different code optimization techniques on software power, performance and code size