Title :
A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing
Author :
Khailany, Brucek ; Williams, Ted ; Lin, Jim ; Long, Eileen ; Rygh, Mark ; Tovey, DeForest ; Dally, William J.
Author_Institution :
Stream Processors, Sunnyvale, CA
Abstract :
A 34M transistor stream processor SoC for signal, image, and video processing contains 80 parallel integer ALUs organized into 16 data-parallel lanes with a 5-ALU VLIW per lane, two CPU cores and I/Os. Implemented in a 0.13mum CMOS technology, sixteen 800MHz data-parallel lanes combine to deliver performance of 512 8b GOPS or 256 16b GOPS.
Keywords :
CMOS integrated circuits; image processing; parallel machines; system-on-chip; video signal processing; 0.13 micron; 16 bit; 8 bit; CMOS technology; data-parallel lanes; image processing; parallel integer ALU; programmable 512 GOPS stream processor; signal processing; system-on-chip; video processing; Bandwidth; Computer architecture; Digital signal processing; Kernel; Registers; Signal processing; Signal processing algorithms; Streaming media; Switches; VLIW;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373399
