• DocumentCode
    2869187
  • Title

    A 64K EPROM using scaled MOS technology

  • Author

    Perlegos, G. ; Pathak, Sant ; Renninger, A. ; Johnson, Wayne ; Holler ; Skupnak, J. ; Reitsma, M. ; Kuhn, G.

  • Author_Institution
    Intel Corp., Santa Clara, CA, USA
  • Volume
    XXIII
  • fYear
    1980
  • fDate
    13-15 Feb. 1980
  • Firstpage
    142
  • Lastpage
    143
  • Abstract
    This paper will report on a 64Kb static MOS EPROM which combines a two-layer poly self-aligned memory cell together with scaled NMOS periphery technology. Cell size is 0.24μm2/b. Access time is 200ns.
  • Keywords
    Circuits; EPROM; Electrons; Geometry; MOSFETs; Microprocessors; Nonvolatile memory; PROM; Packaging; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1980 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1980.1156041
  • Filename
    1156041
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2869187