DocumentCode
2869319
Title
A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process
Author
Desai, Shaishav ; Trivedi, Pradeep ; Von Kanael, V.
Author_Institution
P.A. Semi, Santa Clara, CA
fYear
2007
fDate
11-15 Feb. 2007
Firstpage
308
Lastpage
605
Abstract
A 0.2-to-4GHz PLL generates the clock for an SoC in a 65nm CMOS process. The PLL uses dual-oxide devices operating in different voltage domains to generate a clock with a wide range of output frequencies and low jitter. The measured rms period jitter is 1.5ps at 2GHz and total power consumed from both the 1.0V and 1.8V supplies is 15mW.
Keywords
CMOS integrated circuits; clocks; jitter; phase locked loops; system-on-chip; 0.2 to 4 GHz; 1.0 V; 1.8 V; 15 mW; 65 nm; CMOS process; clock generators; clock multiplier; phase locked loops; system-on-chip; CMOS process; Clocks; Counting circuits; Frequency; Jitter; Phase locked loops; Regulators; Solid state circuits; Voltage; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0853-9
Electronic_ISBN
0193-6530
Type
conf
DOI
10.1109/ISSCC.2007.373417
Filename
4242388
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