Efficient modeling of metal fill parasitic capacitance in on-chip transmission lines

We present a general modeling methodology for metal fill parasitic capacitance in on-chip transmission lines. Our approach is based on reducing the problem complexity in all three dimensions. Typical speed-up is 16 fold. The maximum error in self and mutual capacitance is < 6 % and < 10 %, respectively over a wide range of parameters. The agreement with measurements is within 2.1 %. We predict the slow-wave factor of transmission line designs with < 1.2 % error and Q degradation with < 4 % error.