A 62μA Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer

Author

Paavola, Matti ; Kämäräinen, Mika ; Järvinen, Jere ; Saukoski, Mikko ; Laiho, Mika ; Halonen, Kari

Author_Institution

Helsinki Univ. of Technol., Espoo

fYear

2007

fDate

11-15 Feb. 2007

Firstpage

318

Lastpage

605

Abstract

An interface ASIC for a capacitive 3-axis micro-accelerometer is implemented in a 0.13μm CMOS process. Die area and power dissipation are reduced by using time-multiplexed sampling and duty cycles down to 0.3%. The chip with 0.51 mm² active area draws 62μA from a 1.8V supply while sampling 4 proof masses, each at 1 kS/s. With a plusmn4g capacitive 3-axis accelerometer, the measured noise in the x, y and z directions is 460μg/radicHz, 550(μg/radicHz and 550μg/radicHz, respectively.

Keywords

CMOS integrated circuits; accelerometers; application specific integrated circuits; detector circuits; low-power electronics; 0.13 micron; 1.8 V; 62 μA; CMOS process; capacitive 3-axis micro-accelerometer; duty cycles; interface ASIC; time-multiplexed sampling; Acceleration; Accelerometers; Application specific integrated circuits; Clocks; Differential amplifiers; Frequency; Power dissipation; Resistors; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0852-0

Electronic_ISBN

0193-6530

Type

conf

DOI

10.1109/ISSCC.2007.373422

Filename

4242393