• DocumentCode
    2870542
  • Title

    MOS buried load logic

  • Author

    Sakai, Yoshiki ; Masuhara, T. ; Minato, O. ; Hashimoto, Noriaki

  • Author_Institution
    Hitachi Central Research Laboratory, Tokyo, Japan
  • Volume
    XXIII
  • fYear
    1980
  • fDate
    13-15 Feb. 1980
  • Firstpage
    56
  • Lastpage
    57
  • Abstract
    A MOS buried logic technique using buried JFET loads with a gate delay of 0.34ns and a power delay product of 0.17pJ will be reported. Development has been applied to a 4-stage binary counter operating with a maximum toggle of 72.4MHz.
  • Keywords
    CMOS technology; Counting circuits; Delay; Electron devices; Frequency; Inverters; Logic; Physics; Power dissipation; Solid state circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1980 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1980.1156123
  • Filename
    1156123
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2870542