A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current

Author

Hanzawa, Satoru ; Kitai, Naoki ; Osada, Kenichi ; Kotabe, Akira ; Matsui, Yuichi ; Matsuzaki, Nozomu ; Takaura, Norikatsu ; Moniwa, Masahiro ; Kawahara, Takayuki

Author_Institution

Hitachi, Tokyo

fYear

2007

fDate

11-15 Feb. 2007

Firstpage

474

Lastpage

616

Abstract

An experimental 512kB embedded PCM uses a current-saving architecture in a 0.13μm 1.5V CMOS. The write scheme features a low-write-current resistive device and achieves 416kB/s write-throughput at 100muA cell current. A charge-transfer direct-sense scheme has a 16b parallel read access time of 9.9ns in an array drawing 280μA. A standby voltage scheme suppresses leakage current in the cell current path and increases the measured PCM cell resistance from 3 to 33MΩ.

Keywords

CMOS memory circuits; embedded systems; leakage currents; phase change materials; 0.13 micron; 1.5 V; 100 μA; 16 bit; 280 μA; 3 to 33 Mohm; 416 kbit/s; 512 kbit; 9.9 ns; CMOS integrated circuits; cell write current; charge-transfer direct-sense scheme; current-saving architecture; embedded phase change memory; leakage current; low-write-current resistive device; Current measurement; Electrical resistance measurement; Leakage current; MOSFETs; Phase change materials; Phase change memory; Preamplifiers; Testing; Throughput; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

1-4244-0852-0

Electronic_ISBN

0193-6530

Type

conf

DOI

10.1109/ISSCC.2007.373500

Filename

4242471