Title :
A 65nm 1Gb 2b/Cell NOR Flash with 2.25MB/s Program Throughput and 400MB/s DDR interface
Author :
Villa, Corrado ; Vimercati, Daniele ; Schippers, Stefan ; Polizzi, Salvatore ; Scavuzzo, Andrea ; Perroni, Maurizio ; Gaibotti, Maurizio ; Sali, Mauro Luigi
Author_Institution :
STMicroelectronics, Palermo
Abstract :
A 1.8V 1 Gb 2b/cell NOR flash memory is based on a time-domain voltage-ramp reading concept and designed in a 65nm technology. The program method, architecture and algorithm to reach 2.25MB/S programming throughput are presented. The read concept allows 70ns random access time and a 400MB/S sustained read throughput via a DDR interface
Keywords :
NOR circuits; flash memories; 1 Gbit; 65 nm; 70 ns; DDR interface; NOR flash memory; time-domain voltage-ramp reading; Clocks; Flash memory; Logic programming; Master-slave; Multiplexing; Nonvolatile memory; Protection; Throughput; Time domain analysis; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
1-4244-0853-9
Electronic_ISBN :
0193-6530
DOI :
10.1109/ISSCC.2007.373501
