DocumentCode
2870771
Title
A DLL with Jitter-Reduction Techniques for DRAM Interfaces
Author
Kim, Byung-Guk ; Kim, Lee-Sup ; Park, Kwang-Il ; Jun, Young-Hyun ; Cho, Soo-In
Author_Institution
KAIST, Daejeon
fYear
2007
fDate
11-15 Feb. 2007
Firstpage
496
Lastpage
497
Abstract
A DLL featuring jitter-reduction techniques for a noisy environment is described. Loop behavior is controlled by monitoring the amount of jitter caused by supply noise of a replica delay line. The DLL is implemented in a 0.13mum CMOS process, and at 1 GHz, it has 4.58psrms jitter and 29pspp jitter with noisy replica delay line.
Keywords
CMOS integrated circuits; DRAM chips; delay lines; delay lock loops; jitter; 0.13 micron; 1 GHz; CMOS process; DLL; DRAM interfaces; delay-locked loop; jitter-reduction techniques; noisy environment; replica delay line; supply noise; Bandwidth; Clocks; Convergence; Delay lines; Frequency; Jitter; Random access memory; Solid state circuits; Space vector pulse width modulation; Tracking loops;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
1-4244-0853-9
Electronic_ISBN
0193-6530
Type
conf
DOI
10.1109/ISSCC.2007.373511
Filename
4242482
Link To Document