DocumentCode
2870899
Title
Computer architecture using NMOS technology
Author
Druke, M. ; Buckley, Erin ; Gusowski, R. ; Carberry, D. ; Feaver, R. ; March, R.
Author_Institution
Data General Corp., Westboro, MA, USA
Volume
XXIII
fYear
1980
fDate
13-15 Feb. 1980
Firstpage
110
Lastpage
111
Abstract
A family of NMOS devices for a CPU chip which executes 16-bit register-to-register operations in a single 400ns microcycle, and memory-to-register moves in 2 microcycles, will be described.
Keywords
Computer architecture; Kernel; Logic; MOS devices; Microcomputers; Pipelines; Protection; Random access memory; Registers; System buses;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1980 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1980.1156143
Filename
1156143
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