DocumentCode
2873640
Title
A 35ns 16K NMOS static RAM
Author
Anami, K. ; Yoshimoto, Masahiko ; Shinohara, Hirofumi ; Hirata, Yasuhisa ; Harada, Hiroshi ; Nakano, T.
Author_Institution
Mitsubishi Electric Corporation, Itami, Japan
Volume
XXV
fYear
1982
fDate
10-12 Feb. 1982
Firstpage
250
Lastpage
251
Abstract
An NMOS 16K×1b static RAM optimized for low soft error sensitivity will be discussed. Access time is typically 35ns with a 275mW active power dissipation.
Keywords
Capacitance; Circuits; Decoding; Impedance; MOS devices; Power dissipation; Read-write memory; Temperature; Transient analysis; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1982.1156309
Filename
1156309
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