Title :
A 72Kb bipolar DRAM
Author :
Houghton, R. ; Boulay, P. ; Penoyer, R.
Author_Institution :
IBM Corp., Essex Junction, VT, USA
Abstract :
A TTL-compatible 72Kb bipolar DRAM chip (8K×9), with data stored on the junction capacitance of a 200μm2dielectric-isolation cell, will be described. The chip operates at 50ns access and 150ns cycle times.
Keywords :
Buildings; Dielectric substrates; Fault location; Integrated circuit interconnections; Latches; Physics; Random access memory; Resistors; Solid state circuits; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1982.1156389
