• DocumentCode
    2875154
  • Title

    A bit-serial VLSI processor for kernel-based classifiers

  • Author

    Madrenas, J. ; Moreno, J.M. ; Cabestany, J. ; Seco, J.

  • Author_Institution
    Dept. d´´Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
  • fYear
    1996
  • fDate
    4-6 Sep 1996
  • Firstpage
    549
  • Lastpage
    558
  • Abstract
    A bit-serial digital VLSI processor that emulates the operation of kernel-based classifiers is described. First the operating principle and the relevant characteristics of that kind of neural classifiers are introduced. Operations are identified and suitable approximations are proposed in order to make the required computations compatible with a digital VLSI implementation. Then, the bit-serial processor architecture is described. Basically it consists of three modules: distance calculation, kernel function approximation and accumulation-comparison. Estimated results on area, processing speed and power consumption of a synthesized ASIC are given in comparison with a published analog processor. The obtained data show that the reported approach is very promising for high throughput applications
  • Keywords
    VLSI; application specific integrated circuits; function approximation; neural chips; pattern classification; ASIC; accumulation-comparison; bit-serial VLSI processor; distance calculation; kernel function approximation; kernel-based classifiers; neural classifiers; operating principle; Computer architecture; Energy consumption; Function approximation; Iterative algorithms; Kernel; Network synthesis; Neural networks; Prototypes; State estimation; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Neural Networks for Signal Processing [1996] VI. Proceedings of the 1996 IEEE Signal Processing Society Workshop
  • Conference_Location
    Kyoto
  • ISSN
    1089-3555
  • Print_ISBN
    0-7803-3550-3
  • Type

    conf

  • DOI
    10.1109/NNSP.1996.550062
  • Filename
    550062