• DocumentCode
    2876285
  • Title

    Gemini NI: An Integration of Two Network Interfaces

  • Author

    Wang, Kai ; Li, Xiaomin ; An, Xuejun ; Sun, Ninghui

  • Author_Institution
    Nat. Res. Center for Intell. Comput. Syst., Chinese Acad. of Sci., Beijing, China
  • fYear
    2009
  • fDate
    9-11 July 2009
  • Firstpage
    439
  • Lastpage
    446
  • Abstract
    According to the development of the TOP500, the performance of the high performance computers (HPCs) is increasing rapidly. The incredible performance increment of the HPCs should be largely attributed to the development of their communication systems, because the HPCs cannot extend to such a large scale without their excellent communication systems. As an important member of the communication system, the network interface (NI) always plays a significant role. Since the network interface locates on the critical path of the communication system, it can easily become a bottleneck if it cannot provide low latency and high bandwidth for communication. The Gemini NI presented in this paper has a good performance potential in both latency and bandwidth. It has a remote load/store (RLS) mechanism which can provide ultra low latency. Furthermore, it has two HyperTransport (HT) interfaces connected to double processors or symmetric multi-processors (SMP), and it has four proprietary switch interfaces connected to the switches. This approach largely in-creases the throughput of the Gemini NI. Inside the Gemini NI, almost all the components of a network interface are duplicated. The resource sharing within the Gemini NI can provide great flexibility for scheduling. A FPGA prototype of the Gemini NI has been implemented, and the preliminary results prove the validity of our design.
  • Keywords
    field programmable gate arrays; multiprocessing systems; network interfaces; processor scheduling; FPGA prototype; Gemini NI; TOP500; communication systems; high performance computers; hypertransport interfaces; network interfaces; remote load/store mechanism; scheduling; switch interfaces; symmetric multiprocessors; Bandwidth; Delay; Field programmable gate arrays; High performance computing; Large-scale systems; Network interfaces; Resonance light scattering; Resource management; Switches; Throughput; Gemini NI; HPP; RDMA;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Networking, Architecture, and Storage, 2009. NAS 2009. IEEE International Conference on
  • Conference_Location
    Hunan
  • Print_ISBN
    978-0-7695-3741-2
  • Type

    conf

  • DOI
    10.1109/NAS.2009.74
  • Filename
    5197361