Digital phase-locked loop for frequency distribution over packet networks

This paper describes a digital phase-locked loop (DPLL) for frequency synchronization over packet networks. This timestamp-based technique for frequency synchronization involves a transmitter clock sending periodically an explicit time indication or timestamp to the receiver so that it can synchronize its local clock to that of the transmitter. The digital oscillator used in the PLL is a divide-by-N counter type oscillator (DNCO). We explain how the DPLL can be designed using standard control theory concepts and show how the loop filter gains are readily obtained given known/specified loop components such as phase detector and DNCO and a set of DPLL performance specifications.