Challenges of Thin Core Substrate Flip Chip Package on Advanced Si Nodes

Advanced silicon node is becoming the mainstream technology used for electronic product and flip chip package is one of the assembly solutions to meet of high-end products requirement. For flip-chip assembly application, reducing the core thickness of substrate to derive higher electrical performance and routing density has been approached. Combining with lower mechanical strength characteristics of low-k dielectric material, the management of thin-core substrate warpage and the stress to low-k dielectric has become the challenges to manufacture a robust and reliable advanced flip-chip product. In this paper, mechanical saw optimization and pre-solder height control on C4 pad of substrate have been evaluated. The warpage change at each major process step of flip-chip assembly process has been measured. Through the numerical analysis, all the critical factors are analyzed to understand their effect [1], and pre-conditioning followed by temperature cycling test proves the optimized design. The experiment results showed the underfill and die thickness have significant impact to package warpage and stress to low-k, which is matched with simulation predictions. To 400 um thin-core substrate, 787 um (31 mil) silicon die combining lower Tg (<80degC/TMA) underfill could perform better package warpage and competitive stress level.